1. Field of the Disclosure
This disclosure relates generally to high-voltage nonvolatile memory arrays and high-voltage page buffers. More specifically, this disclosure relates to the novel methods and apparatus for improving the operations of those popular NVM arrays with their cells employing the similar write scheme of high-voltage (HV) but low-current Fowler-Nordheim (FN) channel-erase and FN channel-program to allow using the very compact low-voltage (LV) page buffer and smaller HV charge-pump circuit for achieving drastic reduction in both die size and power consumption in write operation.
2. Description of Related Art
Nonvolatile memory (MVM) is well known in the art. For those NVMs that provide the repeatedly in-system or in-circuit electrically programmable and erasable functions today include the three major standalone NVMs such as EEPROM, NOR Non-volatile Memory, and NAND Non-volatile Memory plus one Embedded (em) Non-volatile memory that comprises of varied technologies.
The major NVM cell and the cell array structures and operations are all different. The mainstream NVMs of NAND, NOR, Embedded NOR and EEPROM bells are either made of 2-poly floating-gate NMOS or 1-poly charge-trapping NMOS storage devices. In a charge trapping mechanism, as in a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) or Metal-Oxide-Nitride-Oxide-Silicon (MONOS) type cell, the charge is trapped in a charge trapping layer between two insulating layers. The charge trapping layer in the SONOS/MONOS devices has a relatively high dielectric constant (k) such Silicon Nitride (SiNx).
Currently, the mainstream standalone NAND and EEPROM NVMs in mass production are mainly based only the 2-poly floating-gate NMOS device. Both NAND and NOR NVMs designs are employing the HV, extremely low current FN channel-erase and FN channel-program.
But the NOR standalone non-volatile memory has two major kinds of the cell structures. One unique standalone NOR non-volatile design is using NMOS 1-poly charge-trapping cell by one single company such as Spansion. The remaining NOR non-volatile companies are using the similar 2-poly floating-gate NMOS cell in production today. These companies include a US company, Micron, and one company in Korea, Samsung, and two other Taiwanese companies such as Macronix and Winbond. As opposed to NAND non-volatile memory, both NOR non-volatile cells, regardless of 2-poly or 1-poly cell structures, are using the same high-current channel hot-electron (CHE) like EPROM cell for programming but using extremely low current FN channel for erasing operation.
For embedded NOR cells, there are also two kinds of cells. One is like the Silicon Storage Technology's (SST) Superflash split-gate cell that is using low-current CHE for program but extremely low current FN tunneling between top two Polys for erase operation. The cell structure and operating conditions are shown in Figures DD and SS.
The other two popular emFlash solutions are like NAND approaches employing both extremely low current scheme of the FN channel erase and FN channel program. These two companies are Infineon and Cypress semiconductor companies. Infineon approach is adopting the 2-poly floating-gate NAND-like, 1 T emFlash cell structure, while Cypress is using 1-poly, charge-trapping, 1-poly, NAND-like cell structure. The cell's circuit and operating conditions are shown in Figures of XX and YY.
For all above mentioned different NVMs and their associated with cells' operation conditions, erase is common using the extremely low current FN channel program, which is not the topic of this disclosure. This disclosure is fully focusing on those NVM cells and cell arrays that are employing the HV but extremely low current FN program operation. More particularly, the focus of this disclosure is to provide a novel approach for the fast and low-current program and program-inhibit operations so that the saving of the power consumption can be achieved. The invented approach of the present disclosure can be applied to all NMV cells that are using the extremely low current FN-channel erase and FN-channel program. These referred cells include today's mainstreamed Standalone NAND flash memory from Toshiba, Samsung, Micon and Hynix and the embedded Flash (emFlash) cells such as Infineon and Cypress, regardless of 1-poly or 2-poly cell, or PMOS or NMOS, 2D or 3D cell structures.
The reason that the Standalone NOR cells such as from Micron multi-level cell (MLC) ETOX cell, Spansion Mirror-bit cell and SST Superflash cell cannot be applied with this disclosure because they have a common issue of the conduction current between the cell's Drain-Source channel during the Program and Program-Inhibit operation. In extremely low current FN channel-erase and FN-channel program there is no conduction current between cell's drain-source channel, thus the cell array inhibit current in BLs or SLs can be eliminated; thus the program Inhibit operation can be normally operated without resulting any failure.
Further because this novel program and Program-Inhibit method, the traditional on-chip large, non-scalable HV page buffer can be replaced by a small, compact LV page buffer design for die size reduction. Furthermore, the traditional on-chip HV charge-pump must be active all the times during the program and program inhibit operations can only be needed in the beginning charge-up cycles and can be shut off for drastic power-saving.